A ROM, the storage contents of memory cells of which can be electrically erased and changed, is known as an EEPROM (electrically erasable programmable ROM). When compared with an EPROM, EEPROM can be used more easily since data are erased with electric signals while being mounted on a circuit board, so that demands for use with various control circuits, memory cards or the like are rapidly increasing. A large scale EEPROM in particular which is used when changing data in a floppy disk has been recently desired.
FIGS. 1A to 1C show the structure of the memory array of a conventional NAND type EEPROM suitable for large scale integration. FIG. 1A is a plane view of the pattern, FIG. 1B is a cross section along line A--A' of FIG. 1A, and FIG. 1C is a cross section along line B--B' of FIG. 1A. Referring to FIG. 1A, a portion enclosed by a broken line and indicated at 10 represents one NAND basic block. As understood from FIG. 1B, this NAND basic block 10 is partitioned from other NAND basic blocks disposed in the right/left direction as viewed in FIG. 1B by field oxide films 12, 12, . . . The vertical cross section of the NAND basic block 10 is as shown in FIG. 1C. Specifically, referring to FIG. 1C in particular, reference numeral 11 represents a p-type silicon semiconductor substrate, 13 a common source region made of an n.sup.+ diffusion layer and shared by respective basic blocks 10, 14 a drain region of the NAND basic block 10 which region is also made of an n.sup.+ diffusion layer, 15, 15, . . . source/drain regions of memory cells within the NAND basic block 10 which regions are made of n.sup.+ diffusion layers, 16, 16, . . . floating gates made of a first polysilicon layer, 17, 17, . . . control gates made of a second polysilicon layer, 18 a first select gate constructed by electrically connecting together the first and second polysilicon layers, 19 a second select gate constructed by electrically connecting together the first and second polysilicon layers, 20 a data line, 21 a contact connecting the drain region 14 and the data line 20, 22 a gate oxide film formed between the floating gate 16 and the substrate 11 and having a thickness of, e.g., about 100 .ANG., 23 a gate insulating film formed between the floating gate 16 and the control gate 17 for which the film has a thickness of about 300 .ANG. and a three-layered structure of, e.g., ONO (oxide-nitride-oxide), 24 an insulating oxide film, and 25 and 26 gate oxide films formed between the substrate 11 and the first and second select gates 18 and 19, respectively, and having a thickness of, e.g., about 400 .ANG.. This gate oxide film 25 may be of the ONO three-layered structure which is formed at the time of forming the gate oxide film 23. In this case, the select gate transistors 18 and 19 are made of only the second polysilicon layer without using the first polysilicon layer. As seen from FIG. 1C in particular, each NAND basic block 10 is formed with ten transistors (memory cells and select gate transistors) 31 to 40 which will be described later in detail. The transistors 31 to 40 are turned on and off by means of gates 17 to 19 of respective channels. The on/off of the transistors 32 to 39, however, is controlled in dependence upon whether each floating gate 16 has electrons or holes.
Each floating gate 16 stores "1" or "0" in dependence on whether it has electrons or holes.
The number of control gates 17, 17, . . . provided for each NAND basic block 10 is, for example, eight. Each control gate is formed continuously to cover a plurality of floating gates 16, 16, . . . positioned under the control gate. Namely, as seen from FIGS. 1A and 1B in particular, the width (width in the up/down direction as viewed in FIG. 1A) of each floating gate 16, 16, . . . is the same as that of each control gate 17, 17, . . . , and the length (length in the right/left direction as viewed in FIG. 1A) of each floating gate 16, 16, . . . is formed shorter than the width of each NAND basic block. The memory cell array is constructed by disposing the NAND basic blocks 10 in matrix in the up/down right/left directions as viewed in FIG. 1A.
The equivalent circuit of the NAND basic block 10 is shown in FIG. 2. In FIG. 2, two NAND basic blocks 10 and 10 disposed right and left are shown. As seen from FIG. 2, the equivalent circuit of each NAND basic block 10 is constructed such that between the source 13 and the data line 20 (DL1, DL2), the select gate transistor 31, eight memory cells 32 to 39, and select gate transistor 40 are serially connected. The transistors 31 and 40 are inputted with select gate signals SG1 and SG2, respectively, and word lines WL1 to WL8 are connected to the control gates 17 of the memory cells 32 to 39.
The data erase/write operation of eight memory cells 32 to 39 each made of a floating gate transistor will be described hereinbelow.
As understood from FIG. 3A, data are erased by applying a high voltage, e.g., 15V to the control gate 17 and connecting the source 15 and drain 15 to a 0V ground potential. By applying a high voltage to the control gate 17, the control gate 17 and the floating gate 16 are electrostatically coupled so that the potential of the floating gate 16 rises and electrons are injected from the source 15 or drain 15 into the floating gate 16 via the gate oxide film 22. This is called an erase state, and the stored data at this state is defined as a "1" level. The threshold voltage of the memory cell at this state becomes about 2 to 3V as shown in the characteristic curves of FIG. 4.
As understood from FIG. 3B, data are written by setting the control gate 17 at 0V, making the source 15 in an open state, and applying a high voltage to the drain 15. In this case, electrons are emitted to the drain 15 from the floating gate 16, and the threshold voltage of the memory cell becomes about -5V as shown in the characteristic curves of FIG. 4. The stored data at this state are defined as a "0" level.
The operation of the NAND basic block 10 show in FIGS. 2 and 1A will be described with reference to Table 1.
TABLE 1 __________________________________________________________________________ ORDER OF WRITING DATA CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 CELL 8 READ ERASE (32) (33) (34) (35) (36) (37) (38) (39) (EXAMPLE) __________________________________________________________________________ SG2 15 V 20 V 20 V 20 V 20 V 20 V 20 V 20 V 20 V 5 V WL8 15 20 20 20 20 20 20 20 0 5 WL7 15 20 20 20 20 20 20 0 0 5 WL6 15 20 20 20 20 0 0 0 0 5 WL5 15 20 20 20 20 0 0 0 0 5 WL4 15 20 20 20 0 0 0 0 0 5 WL3 15 20 20 0 0 0 0 0 0 5 WL2 15 20 0 0 0 0 0 0 0 5 WL1 15 0 0 0 0 0 0 0 0 0 SG1 5 0 0 0 0 0 0 0 0 5 DL1 0 20 20 20 20 20 20 20 20 1 DL2 0 10 10 10 10 10 10 10 10 0 __________________________________________________________________________
Data are erased by setting the data line DL1, DL2 to 0V, SG1 to 5V, SG2 to 15V, and word lines WL1 to WL8 to 15V. In this state, all the drains and sources of the memory cells 32 to 39 become 0V so that all the data in the memory cells 32 to 39 are erased collectively.
Data are written sequentially and selectively starting from the memory cell 32 (cell 1) nearest to the select gate transistor 31. First, in order to write data in the cell 32, SG1 is set to 0V, data line DL1 to 20V, DL2 to 10V, and SG2 to 20V. Next, word line WL1 is set to 0V, and all the other word lines WL2 to WL8 to 20V so that the memory cell 32 is selected and data are written therein. The threshold voltage of the memory cell whose data have been erased is about 3V, whereas that of the memory cells 33 to 39 (cell 2 to cell 8) with a high voltage being applied in a write state is about 5V while taking the substrate effect into consideration. As a result, the drain of the memory cell 32 is applied with (gate voltage of the memory cell 33)--(threshold voltage of the erased memory cell)=(20V -5V)=15V, so that electrons are emitted from the floating gate to the drain via the gate oxide film (indicated at 22 in FIG. 1B) having a thickness of 100 .ANG., in other words, data are written in the memory cell 32.
In writing data in the next memory cell 33, word Lines WL1 and WL2 are set to 0V, and all the other word lines WL3 to WL8 are set to 20V. In a similar manner, data writing is sequentially performed up to the memory cell 39 with voltages being set as shown in Table 1.
If data are not written in a selected memory cell, i.e., if the "1" level data are remained unchanged, data line DL1 is applied with 0V or 10V instead of 20V. In this case, a voltage is not applied between the floating gate and the drain, or an applied voltage is small, so that data are not written.
As described above, data writing is sequentially performed for eight memory cells starting from the memory cell 32 on the source side. The reason for this is that if data are written into a cell without using this data writing order, a high voltage (20V) is applied to the word lines of the other cells already written, and 0V is applied to the drain, to thereby produce an erase state and erase the data in the other cells. By using the above-described data writing order, it is possible to prevent the written data from being erased.
Furthermore, while a data erase/write operation is carried out for the block 10 on the data line DL1 side, the other data line DL2 is applied with about 10V which is an intermediate voltage between the write and erase operations. This is carried out for preventing erroneous data erase/write relative to the memory cells connected to the data line DL2.
Furthermore, while one NAND basic block is selected and data are written, in the other NAND basic blocks connected to the block vertically (in the up/down direction as viewed in FIG. 1A), SG2 is set to 0V and the word lines WL1 to WL8 are set to 0V so as to prevent erroneous data erase/write.
The data read operation from the NAND basic block is carried out in the following manner. For example, in FIG. 2, consider the case wherein data are read by selecting the memory cell 32 in the NAND basic block connected to the data lines DL1. In this case, as shown in Table 1, DL1 is set to 1V, SG1 and SG2 to 5V, the selected word line WL1 to 0V, and the other word lines WL2 to WL8 to 5V. The non-selected data line DL2 becomes a floating state, and takes approximately 0V. If the stored data in the selected memory cell 32 are of the "1" level (threshold voltage of +3V), the control gate voltage is 0V so that it takes an off-state. As a result, in the selected NAND basic block 10, current will not flow between the data line DL1 and the ground potential so that the "1" level data are sensed with a sense amplifier (not shown) connected to the data line DL1. On the other hand, if the stored data in the selected memory cell 32 is of "0" level (threshold voltage of -5V), the memory cell 32 takes an on-state even if the control gate voltage is 0V. In this case, the control gate voltages of the other memory cells 33 to 39 are 5V and these memory cells 33 to 39 take an on-state irrespective of the stored data. Therefore, in this basic block, current flows between the data line DL1 and the ground potential so that the "0" level data are sensed with the sense amplifier.
In a conventional memory having NAND basic blocks described above, memory cells can be disposed at the pitch of the word lines (control gates 17), and only a single contact 21 is used for a plurality (e.g., eight) of memory cells, allowing a larger number of memory cells per unit area and providing a structure suitable for miniaturizing a large capacity memory. A conventional memory, however, has the following problems.
A first problem is as follows. Since a NAND basic block has a HAND type cell structure with a plurality of memory cells connected in series, it is necessary for reading data from a selected memory cell to turn on other non-selected and erased memory cells. It becomes necessary to therefore turn them on by using a 5V gate voltage and to maintain the threshold voltage smaller than or equal to about 3V (at least smaller than or equal to 5V). Similarly, it is also necessary to maintain the threshold voltage of the selected and erased memory cell larger than or equal to about 1V (at least larger than or equal to 0V). It is difficult however, to uniformly erase all memory cells of a large capacity memory of large scale such as 1M bits or 4M bits as variation will necessarily occur. If such variation causes the threshold voltage of even one erased memory cell to move out of the range from 0V to 3V, then the memory becomes a defective one. It is very difficult to design and manufacture a memory capable of uniformly and reliably erase the data of all memory cells.
Apart from the above, in order to speed up the data read speed, it is necessary to make a larger current flow in a NAND basic block which includes a memory cell storing "0" level data. Also in this case, if the threshold voltage of a non-selected memory cell whose gate is applied with 5V, is 3V, it is not possible to make an on-current sufficiently large. For instance, in a NAND basic block designed on the basis of a 1 .mu.m rule, a cell current only in the order of several .mu.A flows during data reading, which is not suitable from the standpoint of increased speed.
A second problem of a conventional memory is the necessity of high voltage withstanding. During data writing into the memory cell 32 for example, the threshold voltage of the memory cells 33 to 39 is about 5V so that a high voltage of 20V becomes necessary to efficiently write data in the memory cell 32. For this reason, a sufficiently high voltage withstand is required for peripheral circuits, while posing another problem of lowering the reliability due to voltage stress applied to memory cells.